
module AM_Modulator
#(
    parameter BASEWIDTH = 10,
    parameter DEPTH=16,
    parameter CARWIDTH=8,
    parameter oWIDTH = 10,
    parameter Fmclk=65000000
)
(
    input wire signed [BASEWIDTH-1:0] i_Baseband_Signal,
    input wire [63:0] i_CarrierFreq,
    input wire i_clk,
    input wire i_rst,

    output wire [DEPTH-1:0] o_WaveAddr,
    input wire signed [CARWIDTH-1:0] i_Carrier,
    output reg signed [oWIDTH-1:0] o_AM_Signal
);

wire signed [BASEWIDTH:0] biased_base;
wire [DEPTH-1:0] DDS_fctrl;
wire signed [(2*oWIDTH)-1:0] MulOut;
wire signed [BASEWIDTH-1:0] exp_carrier;

assign biased_base=i_Baseband_Signal+(1<<(BASEWIDTH-2));
assign 	DDS_fctrl	=(i_CarrierFreq << DEPTH) / Fmclk;
assign exp_carrier={i_Carrier,{(BASEWIDTH-CARWIDTH){i_Carrier[0]}}};
assign MulOut=biased_base*exp_carrier;

always@(posedge i_clk or posedge i_rst) begin
    if(i_rst) begin
        o_AM_Signal<='b0;
    end
    else begin
        o_AM_Signal<=MulOut[(2*oWIDTH)-1:oWIDTH];
    end
end


DirectDigitalSynthesizer 
#(
    .DEPTH(DEPTH)
)
DDS_CarGen
(
    .i_freq_ctrl(DDS_fctrl),
    .i_phas_ctrl(0),
    .i_clk(i_clk),
    .i_rst(i_rst),
    .o_WaveAddr(o_WaveAddr)
);

endmodule